Co-designing an FPGA-Accelerated Encryption Library With PYNQ: The Pynqrypt Case Study

The number of low-power Internet-connected de-vices has significantly increased in the last decade, mainly due to the proliferation of smartphones and IoT devices. However, strict power constraints and high computational demands in conjunction with the end of fundamental computer science laws have introduced new hardware and software design challenges. Domain-specialized FPGA-based hardware accelerators are a promising approach to overcoming these challenges, providing an excellent tradeoff between performance and flexibility in accelerating complex tasks. However, the required competencies to design hardware accelerators strongly limit their adoption. This paper presents a co-design approach describing the general steps to take while developing a hardware-accelerated kernel using the PYNQ platform for software implementation. We applied the proposed approach using the AES-CTR cipher as a case study, one of the most common algorithms for secure communications and data encryption, showing the benefits that hardware acceleration can bring in constrained scenarios. The reported execution results of our approach demonstrate that exploiting hardware acceleration brings a remarkable execution speed-up while keeping the design complexity low.