High-Swing, Power-efficient, Current-Mode Hybrid Circuit Topologies for Simultaneous Bidirectional Communication

In this work, authors propose high-output voltage swing, power-efficient, echo cancellation hybrid circuit topologies deploying modified current-mode logic (MCML) and dynamic current-mode logic (DCML) circuit topologies for bidirectional simultaneous signaling. The conventional static current-mode logic hybrid (CMLH) circuit topology suffers from high static power consumption due to a fixed tail current source. Moreover, it produces low output differential eye-opening at high data rates. To address the above issues, this work proposes a modified current-mode logic hybrid (MCMLH) and dynamic current-mode logic hybrid (DCMLH) circuit topologies to separate the near-end received signal from the superimposed signal on the interconnect. The proposed hybrid circuit topologies have high output differential eye-opening with moderate power consumption. The proposed hybrid topologies are implemented in 1.2 V, and 65 nm CMOS over a 20 cm FR4-PCB interconnect. The performance results of the proposed MCMLH and DCMLH circuit topologies have energy efficiencies of 0.44 pJ/b and 0.8 pJ/b, respectively, at a 10-Gb/s simultaneous bidirectional (SBD) data rate. The differential eye-opening of the MCMLH and DCMLH hybrid circuit topologies are 1.1 V and 0.8 V, respectively, at 10-Gb/s SBD data rate.