New design of an ultra low power CDR architecture using FDSOI 28 nm technology

In this paper, a new structure of a ring oscillator is proposed to realize an Injection-Locked Ring Oscillator (ILRO) and an Injection-Locked Clock Data Recovery (ILCDR). This circuit is composed of 2 types of inverters based on Fully Depleted Silicon on Insulator (FDSOI) technology. FDSOI technology allows us to implement back-gate auto-biasing feedback without adding transistors and to realize a Quadrature Ring Oscillator (QRO) with an even number of inverters. This new QRO increases the speed of the circuit and is the main block of the injection oscillator. With injection, we can create a low-power ILCDR with low jitter and fast locking time for burst-mode applications. With a Pseudo-Random Binary Sequence (2$^{7}$ PRBS) at 2.4 Gbps, the recovered clock jitter is 4.4 ps (1.1%UIp-p). With a 0.6 V power supply, the power consumption is 978 $\mu A$ (587$\mu$ W).