A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity

In this paper, we present a novel input buffer based on the push-pull architecture for an 11-bit 2-GS/s 8x time-interleaved ADC. The proposed buffer features an auxiliary follower which is used to drive the body terminals of the main push-pull output transistors, removing their non-linear contribution at the output node, with a negligible overhead in terms of power consumption. The ADC features a 0.9-V reference voltage and requires an input common-mode voltage of 0. 45V. The proposed buffer, designed in a 28-nm CMOS technology, achieves better than 73-dB Spurious-Free Dynamic Range (SFDR) in the 1-GHz Nyquist bandwidth, which is up to 6.3dB better than the conventional push-pull topology, burning 38mW from +1.8/-1V supplies, including the bias circuit.