Statically Scheduled vs. Elastic CGRA Architectures: Impact on Mapping Feasibility

Coarse-grained reconfigurable architectures (CGRAs) are programmable hardware platforms with large ALU-like programmable logic blocks and word-wide configurable interconnect. In statically scheduled CGRAs, operations within an application’s dataflow graph (DFG) are scheduled to occur in specific clock cycles. The specific schedule may mandate register insertion on certain DFG edges so that DFG paths are correctly latency balanced. In elastic (dataflow) CGRAs, no scheduling step is executed, as handshaking is used to trigger a specific DFG operation when its inputs arrive. In this work, we present a mapper that can map applications to static and elastic architectures and study the impact of the static vs. elastic paradigms on CGRA mapping feasibility, and specifically, the consequences of these paradigms on the use of CGRA resources in mapped applications. Experimental results, targeting the popular HyCUBE [1] and ADRES [2] CGRA architectures, show that applications mapped onto statically scheduled CGRAs generally require larger array sizes and have longer interconnect paths relative to the same applications mapped onto elastic CGRAs, with the bloat arising from additional registers to balance path latencies.