High-Performance and Power-Saving Mechanism for Page Activations Based on Full Independent DRAM Sub-Arrays in Multi-Core Systems

Modern
DRAM
devices’ performance and energy efficiency are significantly improved when the row-buffer locality is exploited properly. In multi-core architectures, however, the
DRAM
-based main memory banks used by the processing units, called cores, are shared. Memory interference, also known as memory contention, occurs when many cores contend for simultaneous access to the shared banks. The performance benefits provided by utilizing the available row-buffer locality are diminished by the increased memory contention brought on by the integration of more cores. Large
DRAM
page sizes are therefore activated in order to access only a tiny amount of data. Poor energy efficiency or wasted opportunity to loosen
DRAM
power timing restrictions are both downsides to this page over-fetching issue. This study introduces a Fine-Grained Activation (
FGA
) technique to reduce the number of involved bitlines when accessing
DRAM
memory. This technique significantly improves the parallelism at the
DRAM
subarray level to support multiple memory accesses routed to distinct subarrays inside the same memory bank. The
FGA
technique presented in this research intends to provide large energy savings while simultaneously delivering significant performance gains. Our evaluation findings with 4-core multi-program benchmarks demonstrate that the
FGA
technique proposed in this paper can significantly improve both
DRAM
performance and
DRAM
energy efficiency with a negligible area overhead. In comparison to the baseline, the
Half-DRAM
page activation mechanism, and the recently suggested
FGA
mechanism, the proposed technique in this study reduces the average
DRAM
memory access latency for the evaluated four-core applications by 25.6%, 27.1%, and 14.8%, respectively. Our introduced technique also decreases the
DRAM
activation power by an average of 46.7%, 27.1%, and 14.7%, respectively, when compared with the baseline,
Half-DRAM
technique, and the recently proposed
FGA
mechanism.