A Thermally Friendly Bonding Scheme for 3D System Integration

A thermally friendly SoIC bonding scheme, TSV-BPM bonding, is proposed to address the heat dissipation predicament usually encountered in a typical 3D stacking architecture. The bonding interfaces in the heat dissipation path contributes a significant portion of the overall thermal resistance. The proposed TSV-BPM bonding scheme eliminates the bonding pad on the TSV side, so a thinner bonding film is allowed for a lower thermal resistance. A Silicon Thermal Enhancement Module (STEM) with an ultra-thin bonding film is integrated into the modified SoIC structure to further enhance the thermal performance. More than 20% reduction in the overall thermal resistance by adopting a 20% thick bonding film can be expected based on the numerical simulation result. Three critical process steps, including backside planarization for reconstruction, TSV-BPM bonding interface formation, and STEM integration (dielectric thin film bonding), were carefully inspected. The outcomes are encouraging, meaning there is no showstopper to a robust and reliable TSV-BPM bonding result. All the integration processes presented in this study were carried out with low thermal budget to minimize the drift in device performance by the accumulated thermal impact. In addition, the elimination of the bonding pad also results in a significant reduction in the parasitic resistance. The energy required for the inter-chip data movement can thus be significantly cut down, making the proposed TSV-BPM bonding scheme an energy-efficient 3D system integration technology.