Modeling and Analysis of CMOS-based Folded Memristive Crossbar Array for 3D Neuromorphic Integrated Circuits

The scalability of the crossbar array is critical for performing complex computation tasks, as large-scale synaptic arrays are required to complete the operations. To address the drawbacks of a 2D neuromorphic IC, such as long routing paths and large die area, 3D IC technology is considered, where the stacking of the crossbar array enhances the system's scalability. Therefore, a novel crossbar architecture for 3D neuromorphic IC is proposed where the crossbar array is folded to decrease the area by approximately 50%, thereby enhancing the architecture's synaptic density by 50%. In the proposed architecture, CMOS-based memristors are employed, which can be interconnected to the word or bit lines by simple metal lines without using TSVs or MIVs, reducing the crossbar's area and its associated parasitics. Due to the folding of the crossbar layer, the length of the word lines gets reduced by half; therefore, there will be a significant reduction in the parasitics associated with the crossbar, which will help improve the system's performance. A Q3D model of the proposed 3D architecture of the crossbar is designed to extract the parasitics associated with it and to verify and validate the proposed novel concept. An RC circuit model of the proposed architecture is built using the parasitics extracted from the Q3D model to analyze its effect on the system. The circuit is designed in 65nm CMOS technology.