6-Sided Die Protection for Chiplet Package with Multi-Layer RDL

The global Chiplets market forecast for 2021 to 2023 is estimated to reach $47.2B by 2031, expanding at a CAGR of 40.9% during the forecast period. Chiplets provide greater flexibility and integration, enabling compact and thin package that offers an active interposer. Semiconductor manufacturers can choose Chiplets based on their unique requirements such as cost, performance, or power, instead of designing monolithic chips that incorporate all the important elements on a single silicon die [4]. Several factors need to be considered to achieve minimum 2um Line and Space (L/S) requirements of Redistribution Layers (RDL), design rules for Via and Cu Studs to enable successful assembly of Chiplets with 6-sided die protection. Warpage management, process, new equipment, material integrations are key areas to be considered during the development process. We will review the effect of silicon thickness for Chip Attach process, warpage management, multi-layer RDL planarity in relation to underlying polymer planarity, and small die-to-die spacing without incurring EMC void defects. This paper will present a substrate-less Chiplet Test Vehicle of 16mm x 24mm package size with 9 dies including structural silicon dies, 5 layers of RDL and 10um L/S. We will review the key process challenges and steps for creating the 9 die Chiplet with integrated passives on a 300mm round panel as a baseline prior to transferring the Chiplet process to a larger 600mm x 600mm PLP for next generation of 6-sided die protection technology. We will also present Board Level Reliability and cross sections results of the Chiplet package.