Optimum Rc Control and Productivity Boost in Wafer-Level Packaging Enabled by High- Throughput UBM/RDL Technology

The continuous trend in the electronics industry for higher performance devices, increasing power efficiency and miniaturization drives innovations both in front-end-of-line but even more in the field of advanced packaging. Latest developments show that Heterogenous Integration and High- Performance Computing applications require multi-layer and fine pitch packaging designs that push the dimensions of vertical interconnects and redistribution layer (RDL) technologies below 5 micrometers. However, smaller interconnects also define the electrical performance requirements and therefore the contact resistance (Rc) is becoming increasingly important. Additionally, the smaller scaling is in state-of-the-art packaging platforms coupled with higher organic loads that needs to be avoided such as organic or oxide contamination of the metal interfaces. This study presents hardware improvements that facilitate low Rc results (< 2.0 mOhm) on a physical vapor deposition (PVD) platform used in wafer-level-packaging (WLP) for the creation of under bump metallization (UBM) and RDL. The optimization also enables a throughput increase to 80 wafers/hour (WPH). An improved airlock design effectively shrinks pumping and venting times, resulting in a cycle time of approx. 34 seconds per wafer. This allows other processes to be trimmed. Besides, a new indexer rotation concept shortens the chamber-to-chamber transfer by 2 seconds, which reduces the risk to re-contaminate the contact pads at the end of the ICP sputter etch step. The electrical performance relevant for Rc calculation is measured on single-contact Kelvin resistors with via diameters from 25 down to 10 micrometers. Experimental data show for all via diameters considered stable Rc results within a lot at a high-throughput run of 80 WPH.