Formation and 3D Stacking Process of CMOS Chips with Backside Buried Metal Power Distribution Networks

In this paper, we report the formation and 3D stacking process of thin CMOS chips with backside buried metal (BBM) layers. The BBM layer and the signal through silicon vias (TSVs) were simultaneously formed in the Si region of CMOS wafer by thinning of the CMOS wafer, hole formation, trench formation, etching of the bottom SiO
2
layer, low-temperature chemical vapor deposition of SiO
2
film, etchback, Cu filling into the hole and trench, and chemical mechanical polishing. For the backside insulator on the BBM layer, a bisbenzocyclobutene film was used due to its following advantages: (i) photosensitive material, (ii) low curing temperature (453 K), (iii) good adhesion to Cu (BBM layer). In addition, thin CMOS chips with the BBM layers could be stacked by solid-liquid interdiffusion bonding between the frontside and backside bumps. Thus, four-tier stacking of CMOS chips with BBM layers (thickness of each chip: approximately 45 µm) was realized.