3D Stacking of Heterogeneous Chiplets on Modified FOWLP Platform with Thru-Silicon Redistribution Layer

A 3D stacking of CMOS on RF device chiplet is demonstrated for significant reduction of areal form factor for Front-End Module (FEM) application. The salient points of the process integration of thru-silicon redistribution layer on the backside of RF device wafer, chip-to-wafer bonding and assembly, measurement of the interconnection and reliability assessment will be discussed.