Impact of Thermal Annealing and Other Process Parameters on Hybrid Bonding Performance for 3D Advanced Assembly Technology

This paper presents the impact of thermal annealing and other process parameters on hybrid bonding performance in a vacuum anneal batch system and the potential implications for the technology roadmap of 3D chip stacking. The effects of temperature deviation, surface oxidation and sub-atmospheric conditions during annealing, as evaluated by bonding strength and void analysis, on the dielectric film deposited wafers are presented. The excellent within-wafer (WiW) and wafer-to-wafer (WtW) temperature uniformity, much low particle and O2 level, as well as reduced Cu oxide thickness are discussed. The bonding strength of post-anneal dielectric wafers indicated the enhanced capabilities offered by the vacuum annealing, as shown by our investigation and quantification of the effect of temperature deviation from a desired setpoint on bonding strength. In conclusion, we highlight the process improvements offered by the vacuum anneal batch system in meeting some of the challenges associated with 3D chip stacking via enhancements in temperature control, particle performance, minimization of metal ion contamination, and metal oxidation control.