A novel FOWLP method to integrate delicate MEMS components

Fan-Out wafer-level packaging (FOWLP) became widely known for providing an increased surface area compared to wafer-level (chip-scale) packaging at low costs and thus being able to accommodate a greater number of I/O bumps since there are no more restrictions to the die area. Especially the Chips-First Fan-Out technology allows the heterogeneous (co-)integration of sensor elements and corresponding circuitry for even more miniaturized and highly integrated microelectronic packages in IoT and smart devices applications. The protection of delicate sensor areas during compression molding and formation of redistribution layers (RDL) becomes a key challenge of the manufacturing process chain. Such areas include thin membranes, antireflective coatings, air bridges or media access for gas sensors. This paper demonstrates a novel packaging method for a MEMS pressure sensor with corresponding ASIC (application-specific integrated circuit). The package allows a 3D stacking by realizing through package vias (TPVs) based on the integration of vertical interconnect elements (VIE). The increased assembly effort corelates with the low number I/O demands of such a sensor package. The novel Fan-Out approach is, at heart, a hybrid between a Mold-first and RDL-first concept. In contrast to Mold-first concepts, it uses a structured adhesive layer instead of a thermal release tape, onto which components are placed prior to compression molding. Delicate surfaces of MEMS components are not in touch with the adhesive and the cured adhesive after pick and place will protect the surface against the epoxy mold compound (EMC) and die shifting during the process. Due to its thermal and mechanical stability, the patterned thin film adhesive serves as a (first) dielectric layer which also minimizes costs. Process development includes laser de-bonding from temporary glass carriers and RDL processing compatible with delicate MEMS surfaces. Summarizing, this paper presents a novel process variant to avoid common issues related to sensor surface integrity using Fan-Out technology and thus allows for highly miniaturized system in package (SiP) concepts with sensor integration using mold embedding.