Warpage Modulation Study on Panel-level Compression Molding Technology for Heterogenous Integration Applications

Panel-level heterogeneous integration (PHI) can enable new families of architectures with finer bump pitch interconnects for high performance computing (HPC) by taking advantage of panel level advanced packaging infrastructures. As compared to silicon interposers, these emerging architectures are expected to enable more efficient disaggregation / functionality, better power delivery, higher system level bandwidth, larger form factor, and continuous interconnect pitch scaling. Critical few challenges with PHI are to provide: 1) Dimensional stability to enable high patterning lithographical steps with low distortion; 2) Tighter total thickness variation (TTV) control to enable Si bump pitch scaling and redistribution layers (RDLs) with ultra-high density routing. Panel-level compression molding is one of the key enablers for PHI technology to encapsulate bridge dies, as well as top dies after assembly. It is expected to provide dimensional stability as well as tight TTV control across the entire panel post encapsulation. In this paper, we focus on the large form-factor panel-level
$(\sim \mathbf{2600}\mathbf{cm}^{\mathbf{2}})$
compression molding process and identify key process knobs to reduce panel-level and die-level warpage, including material properties, carrier CTEs and die thicknesses. Panel-level and die-level warpage behaviors along the process flow (after bridge die encapsulation, top die attach and overmold) are systematically studied.