Process Integration of Photonic Interposer for Chiplet-based 3D Systems

To overpass the bandwidth and the latency limitations of electrical links, the next breakthrough in high performance computing integration will eventually come through photonic technology and Optical Network-on-Chip (ONoC). This work introduces a global architecture of an ONoC and reports the detail integration and fabrication on the 200 mm Leti's platform of a Si photonic interposer on SOI wafers. Active photonic circuit operating at 1310 nm wavelength, $\mathbf{12}\ \boldsymbol{\mu} \mathbf{m}$ diameter $\mathbf{100}\ \boldsymbol{\mu} \mathbf{m}$ height Through Silicon Via (TSV) middle process, four metal layers Back-End Of Line (BEOL) with $\boldsymbol{\mu}-\mathbf{pillars}$ and backside redistribution layer with thermal cavity above heaters have been successfully achieved. Morphological characterizations as cross-sections assess the process developments and integration results. Optical propagation losses measured on Rib and Deep Rib structures and insertion losses on Single Polarization Grating Couplers (SPGC) structures both at the end of the active photonic and after TSV / BEOL processes show no deviation. The TSV middle resistance is evaluated below $\mathbf{22}\ \mathbf{m}\mathbf{\Omega}$ with a yield greater than 95 %. Finally, all individual process blocks required for the functional ONoC system, especially Ring Modulators is discussed regarding their successful optimized co-integration.