Development of 4 die stack module using Hybrid bonding approach

Die stacking is commonly used in memory modules. Solder micro-bumps and through silicon via (TSVs) are common interconnects, and it may not viable or suitable for device that has bump pitch 10μm or below. Solder interconnects have issues related to brittle intermetallic compound, solder cracked, solder merging, and long duration process if local thermos-compression bonding is adopted. Hybrid Bonding is an attractive approach for die stacking as it can eliminate all the issues of solder interconnects. However, it involves other issues such as stringent surface morphology, demands in high surface's cleanliness, and the need for high temperature annealing process. In this work, we developed processes such as Cu and organic/inorganic dielectrics CMP, Temporary bonding & de-bonding, Damascene Cu process on temporary carrier bonded wafers, and particle free dicing required for chip stacking using Chip-to-Chip/Chip-to-Wafer (C2C/C2W) hybrid bonding. We also demonstrated 4 die stack module using C2C/C2W hybrid bonding approach.