Process Design Kit and Initial Demonstration of Digital Metal-Embedded Chip Assembly for High Density IO Fan-Out Packaging

This paper describes the initial demonstration of a fan-out wafer-level package for high-density input/output (IO) digital CMOS chips using a silicon interposer with an embedded electroplated copper heat spreader. The package uses a redistribution layer (RDL) first chip-last approach featuring multi-layer interconnects that accommodate a minimum chip IO pitch of
$10 \mu \mathrm{m} ((30\mu \mathrm{m}$
demonstrated). The integrated heat spreader simultaneously addresses fine-pitch chip integration, electrical shielding, and thermal management. The process development steps and challenges are discussed, and preliminary electrical results of passive test structures are presented showing
$> 95{\%}$
DC connectivity. The paper also presents the development of a Process Design Kit (PDK) in the Cadence Virtuoso environment for this technology and its application in shortening design time, preventing design rule violations, and extracting RC package parasitics.