Impact of Dielectric and Copper Via Design on Wafer-to-Wafer Hybrid Bonding

Hybrid bonding is key to achieving high-quality interconnect interfaces for fine pitch integration. It has an advantage over other types of interconnects as it allows a high I/O count for high-density memory, increased power and improved signal speed. To achieve high-quality hybrid bonding, Cu interconnects are embedded in the dielectric. The surface is planarized using chemical mechanical polishing. The final CMP process is usually a two-step process involving copper bulk CMP and then barrier CMP. Barrier CMP leads to the final surface finish which is used for hybrid bonding. The final surface has four key surface properties such as copper recess in the vias known as dishing, erosion and roughness of the dielectric layer, and profile change from high-density copper vias towards low-density copper vias. Most of these parameters are tuned using the CMP process. In this work, we present the impact of dielectric on the metal CMP process and look into the atomic force microscopy (AFM) dishing and roll-off behaviour of the interconnect vias, scaling down from 5
$\mu \mathrm{m}$
pitch to 1
$\mu \mathrm{m}$
pitch using silicon oxynitride dielectric as the bonding dielectric.