Reliability Performance on Fine-Pitch SoIC™ Bond

On top of geometry scaling in transistor advancing, chiplet integration technology further improves system performance by 3D IC technology to increase transistor density and bandwidth density. The increases in bandwidth density and energy efficient compute are highly desirable in 5G and AI compute systems. In ECTC 2022, a 3um bond pitch, face-to-face, chip-on-wafer SoIC™ (system on Integrated Chips) system at low thermal budget process was successfully demonstrated. In that study, it was reported that 3um bond pitch SoIC offered a 8X energy efficiency performance (EEP) gain and a 33% Rc reduction as compared to a 9um bond pitch one. To achieve ultra-fine pitch 3D chiplet stacking with high performance, yield and reliability, a seamless integration of tools, materials, design enablement and process control is essential. In this paper, we further present the reliability performance of an ultra-fine pitch, face-to-face, chip-on-wafer SoIC system with < 300°C thermal budget. Test vehicle chips are 6 x 6 mm
²
in size, with full array interconnects. Test patterns for Breakdown Voltage (V
BD
), Electromigration (EM), and Stress-Migration (SM) are designed-in for the reliability evaluation. A finite-element method (FEM) is used to study the failure mechanisms in both EM and SM. The results of EM mean-time-to-failure (MTTF) and Imax are reported. Also, SM characterization study will be presented. The process and design improvements enhancing EM and SM reliability performances are also addressed.