Addressing sub-micron thermal warpage: Industrial application on semiconductor devices

Process stress-induced warpage is a known influencing factor on the electrical and optical behavior of microelectronic devices. Warpage can cause catastrophic failures at the wafer front-end and package assembly level where the various processes (chip thinning, glue attach, interconnection) play a major role in the final die warpage and subsequent final performances. Hence, this parameter must be carefully controlled at different steps of fabrication, including wafer [1], integrated die [3], and product [4]. Imager technologies currently developed by STMicroelectronics face new challenges as it combines chip miniaturization with integration in more and more complex modules, embedding many components. The ability to measure in-situ sub-micron warpage of optical die after packaging, was up-to-then limited by equipment resolution, die size, and Silicon optical properties such as reflectivity. This paper introduces a new thermal warpage technique based on Optical coherence tomography (OCT) [5] to address near flat, transparent, or semi-transparent surfaces and explore its application on optical packages for semiconductor products. OCT distances itself from the conventional Shadow moire and Projection moire methods. These systems require constant relations networking between a source to generate fringe patterns on the surface and a detector. The maximum Z resolution achievable is around 1 μm [6]. But the most challenging are surfaces with high reflectivity or transparent surfaces for which a coating is required. ‘OCT’ simplifies the configuration by the adjustable resolution point-based laser scanning using interferometry, allowing to precisely characterize products such as wafers, imagers, and connectors, without any preparation at a sub-micron level.