Certain Investigation on Adders and Multipliers for Different Applications

The developments in the engineering and research fields demonstrate how low power circuit design has grown in importance. In the past, operating frequency and device density were given more attention than chip power dissipation. Millions of transistors are being crammed onto a chip, though, which increases power dissipation and the processing power of semiconductors as the scale of integration grows. Prior to recently, power dissipation was only given secondary consideration by researchers and designers while creating integrated circuits, with the three main considerations being area, speed, and cost. But in recent years, this situation has altered, and power dissipation reduction through improved circuit design methods is now a significant study topic. The analysis of various multiplier power, area, and delay minimization approaches is the main goal of this research project. Numerous algorithms that reduce the size, power, and delay of multipliers have been studied in the literature; each has pros and downsides in terms of speed, size, and power consumption.