Performance Analysis of Different SRAM Cells and Proposed 9T SRAM Cell

This article presents Designing of SRAM CELL for low power implementations(PROP9T). The presented 9T SRAM cell’s important layout parameters are evaluated using LTSPICE simulations. Comparable findings utilizing conventional 6T (CONV6T), conventional 7T (CONV8T), conventional 8T (CONV8T), conventional 9T (CONV9T), and conventional 10T (CONV10T) SRAM cells are shown with the estimated results. The PROP9T has shown more read delay than CONV6T and CONV8T. Two significant problems with power consumption have been associated with CMOS technology scalability. The problems with 6T, 7T, 8T, 9T, and 10T SRAM cells have been reviewed in this study, and a comparison analysis based on many factors, including read delay, power consumption and write delay has been conducted. The SRAM array structure, which comprises of sensing amplifiers and address decoders, is also included in this study.