Implementation of the Verification process with Universal Verification Methodology in the Computer Systems for the VLSI course

The aim of this paper is to present the improvement of Computer Systems for the VLSI, the 4th-year course at the School of Electrical Engineering, University of Belgrade. This course consisted of only two parts, Software Simulation of DUTs and Synthesis of DUTs on FPGA chips. The UVM Verification of the DUT along with Code-Coverage was added as a third and final part of the course to present the whole design and verification process. Verification with UVM is presented using a simple running example - register with two operations (increment and load). Another improvement of this course is the practical project where students should simulate functional hardware, then Synthesize it on FPGA, and verify it.