On Efficient Hardware Realizations of Fixed-Point Complex Number Magnitude and its Logarithms

The quadrature processing techniques used in digital communications, spectral analysis, and computer graphics demand high-speed calculation of complex number magnitude and its logarithms. The aim of this work is to design a highly parameterizable circuit generator for approximating the magnitude of a complex number and performing the Look Up Table (LUT)-based binary logarithm on its value, thus supporting high-performance data processing. In order to achieve that, Chisel hardware description language has been used. A proposed design generator supports a wide range of parametrization options, including input/output data type and bitwidth, LUT table size, optional square magnitude calculation, several rounding methods, etc. Various generator instances are tested and verified on a commercially available FPGA platform. They are mutually compared in terms of resource utilization and performance.