Extending C/ID Methodology for Optimal Implementation of Single-Stage Discrete-Time Amplifiers

A flow to develop single-stage Discrete-Time (DT) amplifiers based on a set of given requirements, including speed and noise specifications, will be introduced. To reduce the computational complexity of the proposed design flow, C/ID methodology has been employed as the baseline. To demonstrate effectiveness of the proposed design flow, a DT amplifier will be developed to satisfy target performance parameters, namely speed, voltage gain, and noise, when consumption is minimized. The performance of the resulted design shows less than 3% error with respect to the target values. Low complexity of the flow, together with high achievable precision, makes the proposed approach a very appropriate choice for developing analog Electronic Design Automation (EDA) tools.