BBDL: A Wear-Leveling Algorithm of IoT Terminal PCRAM Application

Phase Change Random Access Memory (PCRAM) is a promising non-volatile memory device due to its attractive properties such as low power, fast access time, high storage density and bit addressability. In Internet of Things (IoT) edge computing environment, IoT terminal can greatly improve its storage and computation performance by adopt PCRAM. However, PCRAM suffers from its weakness in endurance. Existing PCRAM wear-leveling researches and proposed algorithms are mainly for storage class main memory architecture and applications. Due to the lack of Memory Management Unit (MMU) in most popular low power IoT terminal Micro Controller Unit (MCU), most existing PCRAM wear-leveling algorithms are not suitable and cannot be used directly in IoT Terminal PCRAM management. Based on our previous research on the storage and computation integrated architecture of IoT terminal, this paper proposes a Block and Bit Double Layer (BBDL) IoT terminal PCRAM wear-leveling algorithm for the first time. A dynamic and static hybrid strategy of block layer and bit layer algorithm is investigated. FPGA based prototype experiments and high level synthesis (HLS) and Simulink based algorithm simulations are carried out. Simulation results show that the proposed BBDL algorithm can effectively improve the endurance of PCRAM in IoT terminal applications.