Designing Future Quantum-Based Nanoelectronics Through Modeling and Simulation [Guest Editorial]

This special issue contains four contributions from leading groups presenting state-of-the-art modeling and simulation of future classical logic and memory devices, which utilize various quantum concepts for their operation. During the past twenty years quantum engineering of classical devices has been mainly responsible for fueling Moore's Law for improving computational power at double transistor density every two years. An introduction of mechanical strain in Silicon devices and corresponding beneficial engineering of electronic bandstructures, dielectric materials with high ionic permittivity, confining transport carriers in narrow body FinFets and tri-gates, and gate-all-around nanowires and nanoribbons, allowed to continue a classical device scaling while meeting low power requirements. Classical devices using a charge degree of freedom as a computational or a memory state had long ago reached sizes where quantum atomistic effects determine device characteristics.