An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and –252 dB FoM

We propose a mm-wave all-digital PLL (ADPLL) based on a new concept of a charge-steering-sampling (CSS) digital phase detection (PD). The CSS-PD operation is formed by first, presetting the input capacitors of a SAR-ADC to $V_{\mathrm{D}\mathrm{D}}$, then discharging them during a reference pulse via a pseudo-differential-pair (pseudo-diff-pair”) directly driven by the oscillator. The differential-mode (DM) charge-residue, representing the phase error, is evaluated by the ADC for supporting the ADPLL operation. This new technique promotes a high PD gain, good isolation of the oscillator, and a multi-bit digital PD output simultaneously, fully benefiting from the advanced CMOS. Further, a digital loop filter (DLF) with a dead-zone (DZ) in the integral path is proposed to avoid any conflicts with the proportional path. Fabricated in 22-nm CMOS, the prototype achieves 75.9 fs RMS jitter, $\lt $-50dBc spur, and -252.4dB FoM from 18.8 to 23.3 GHz.