A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C

A 150-MS/s fully dynamic SAR-assisted pipeline ADC employs a dynamic, bias-free, floating ring amplifier. A Miller negative capacitance scheme overcomes the limited gain of the residue amplifier. Miller negative capacitance requires no extra circuitry and only needs a small capacitance. The measured SNDR and SFDR of the 28-nm CMOS prototype ADC with a 1 V supply are 67.9 dB and 84.3 dB, respectively. The ADC consumes 1.72 mW resulting in a Walden and a Schreier SNDR FoM of 5.7 fJ/conversion-step and 173 dB, respectively.