High Performance 5 nm Si Nanowire FETs with a Record Small SS = 2.3 mV/dec and High Transconductance at 5.5 K Enabled by Dopant Segregated Silicide Source/Drain

The effect of band edge states is the critical issue for cryogenic CMOS, which worsens the performance of conventional MOSFETs at cryogenic temperature (Cryo-T) with saturated subthreshold swing (SS), large transition region (inflection phenomenon) and limited mobility. To address these problems, we fabricated gate-all-around (GAA) Si nanowire (NW) MOSFETs using fully silicided source/drain and dopant segregation. The effect of band edge states is significantly suppressed using this technology. Thus, SS, the effective average $\mathrm{SS_{th}}$ and the transconductance (G
m
) continuously improve as temperature decreases allowing us to achieve high performance NW FETs at 5.5 K with a record small SS of 2.3 mV/dec, ultra-small DIBL of 0.02 mV/V, and high G
m
of 1.25mS/$\mu$m at V
d
= 0.1V.