A 14nm 128Mb Embedded MRAM Macro achieved the Best Figure-Of-Merit with 80MHz Read operation and 18.1Mb/mm² implementation at 0.64V

This paper describes an embedded spin transfer torque magnetic random access memory (STT-MRAM) focusing on minimizing macro area. By exploiting bit write operating condition, a merged source follower write driver (MSWD) is proposed to reduce write driver size and minimize write voltage mismatch. With a boosted pass-gate column mux (BPCM), additional local inverter for switching logic is eliminated. The proposed gated WL driver (GWLD) achieves faster wordline voltage settling time without increasing its size. Cell-based read offset compensation (CROC) is employed to improve read window for high-density memory and low Vdd operation. The proposed MRAM tolerant to solder-reflow process has been fabricated in a 14nmFinFET process, and the area of 128Mb macro is 18.1Mb/mm2. The measurement results show that the proposed MRAM achieves 80MHz read access time in 0.64V core voltage at 150°C temperature.