Demonstration of Recovery Annealing on 7-Bits per Cell 3D Flash Memory at Cryogenic Operation for Bit Cost Scalability and Sustainability

This report is the first to demonstrate cryogenic 3D flash memory of 7-bits per cell with the recovery annealing applied repeatedly. We combined 77 K cryogenic operation and epi-Si channel to improve the data retention, read noise, and program noise, and their degradation caused by Program/Erase (P/E) cycles. We further applied $200 ^{\circ}\mathrm{C}$ annealing which recovers performance degradations under appropriate cell Vth conditions. Reliable 7-bits per cell operation can maintain performance and energy efficiency competitive to current QLC and NL-HDD technologies. Co-optimization of process technology, memory operation, and cooling system is a promising solution for future sustainable bit cost scaling.