Structural Reliability and Performance Analysis of Backside PDN

One of the innovative packaging solutions for beyond-4nm node, Backside-Power Delivery Network (BS-PDN) is investigated to analyze the chip package interaction (CPI) effects. BS-PDN configuration contains dense mircothrough silicon vias $(\mu$TSVs) and power/ground metal stack on the backside of the silicon die. By employing submodeling simulation, stress concentration of this both-side backend-of-the-line (BEOL) structure is analyzed with the node displacement of packaging-level macro model as the boundary condition. Compared to the conventional front-side BEOL structure of current 4nm node, stress concentration is observed in the last Dx metal next to $\mu$TSV in BS-PDN structure for expecting risks of delamination. In addition, we analyze the estimated oscillation frequency of an inverter ring oscillator (INV RO) built using BS-PDN. Effects on the dimension of $\mu$TSVs, materials applied in $\mu$TSVs, and the barrier metal thickness of $\mu$TSVs to suggest the optimal scenario with respect to the CPI risks and RO performance of BS-PDN.