A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS

This work presents a 2.4-to-4.2GHz type-I ring-oscillator-based PLL with wide bandwidth. The switched-capacitor-bias ($\mathrm{I}_{\mathrm{S}\mathrm{C}}$)-based samphng PD ensures the PVT-robustness and high linearity across the wide lock-in range. Due to its merits, the effect of a fast phaseerror correction (PEC) scheme is maximized so that the integrated-jitter is 440.2f$\mathrm{s}_{\mathrm{r}\mathrm{m}\mathrm{s}}$ with 4. 3mW. Furthermore, the optimal varactor (OV)-tuned RO shields the ripple caused by the sampling PD and PEC, resulting in the reference spur of less than -72.8dBc.