A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS

This paper reports a quarter-rate reference-less PAM4 clock and data recovery (CDR) circuit. Our proposed asymmetrical linear phase detector (A-LPD) can simultaneously detect frequency and phase difference for the PAM4 input, thus, fully eliminating the external reference clock or frequency-locked loop. Meanwhile, the presented A-LPD can sense all 12-type PAM4 transitions to reduce the recovered clock’s RMS jitter. An exclusive-OR ring phase-locked loop (XOR-RPLL) is devised for low-power and low-jitter 8-phase clock generation. Fabricated in a 40-nm CMOS, our prototype CDR achieves 231.5-f$\mathrm{s}_{\mathrm{I}\mathrm{m}\mathrm{s}}$ clock jitter, 0.21-pJ/bit energy efficiency, <1$0^{-12}$ bit error rate at 64 Gb/s, and a capture range of 57.2-to-65 Gb/s. Keywords: PAM4, CDR, reference-less, phase detector.