A 2.35 Gb/s/mm2 (7440, 6696) NB-LDPC Decoder over GF(32) using Memory-Reduced Column-Wise Trellis Min-Max Algorithm in 28nm CMOS Technology

For the cost-efficient non-binary low-density parity-check (NB-LDPC) decoder realization, this paper presents a column-wise trellis min-max (CW-TMM) algorithm, greatly relaxing the sorter costs of the previous TMM method without lowering the error-correcting capability. The message compression is used to the trellis-based decoder for the first time, minimizing the memory requirements even for long NB-LDPC codes. In addition, novel circuit-level optimizations are developed to further remove the redundant computing units in the previous works. As a result, the prototype (7440, 6696) decoder over GF(32) in 28 nm CMOS process achieves the normalized area-efficiency of 2.35 Gb/s/mm², saving the decoding complexity and the on-chip memory size by 63% and 54%, respectively.