A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology

To implement ultra-high-speed (UHS) SRAM is a major challenge for high performance computing (HPC) chip. This paper presents BL Charge Time Reduction (BLCTR) with Clamped BL Discharge (CBLD) and Flying Word-Line (FWL) to maximize the SRAM speed. BLCTR with CBLD improves cycle time by decreasing the BL pre-charge time and write time. FWL architecture removes gate loading and accelerates the performance. A test-chip using BLCTR and FWL is fabricated in 4nm FinFET process and demonstrates UHS pseudo two-port SRAM (P2P-SRAM) operating at 4.0GHz.