Thermal consideration in nanoscale gate-all-around vertical transistors

Devolvement of high-performance logic application in sub-20 nm technology node has gained significant attention due to their improved electrostatic and thermal control. In this work, we investigate electro-thermal transport in vertical junctionless nanowire transistors (VNWFET) at cryogenic temperatures to understand thermal effects in nanoscale regime. It highlights that heat dissipation and thermal stability are more efficient compared to planar Finfet configuration.