Influence of Weight Transfer Error on Vector-Matrix Multiplication Using AND Array Architectures

The influence of weight transfer error on vector-matrix multiplication (VMM) in the AND array architecture is investigated. In AND array, a constant voltage is applied to the drain, causing the off-currents of unselected cells connected to the same bitline as the selected cell. The VMM error caused by the off-currents is analyzed and evaluated in AND arrays of varying sizes. The results verify that the current sum error increases proportionally to the square of the number of wordlines (N
WL
).