Physical Understanding on the Anti-fuse Instability to Construct a Selector-Type One-Time-Programming Memory in the High-k Metal-Gate CMOS Generation

A 1kb macro of One Time Programming (OTP) memory, implemented by a novel architecture of a 2T PMOS structure, has been realized on a foundry pure logic 28nm HKMG CMOS platform. The feature size of a unit cell is 2T per cell with 0.04995um
²
. The experimental results show that the designed macro exhibits high programming (PGM) speed of 100ns at 4.6V, the read voltage can be smaller than 1.15V within smaller than 10ns of sense time, and excellent data retention under one-month baking at 150°C. More importantly, it demonstrated high endurance, immunity from the read and program disturbances, which is superior to the mainstream technologies of anti-fuse OTP. This OTP is also expected to be scalable to advanced node such as FinFET and provides an ideal and reliable solution for the hardware security in IoT and 5G era.