Novel Mos2 Dual-Gate FET with a Highly Scaled EOT of ~2.4 nm High-k Gate Dielectric Layer for Reconfigurable Logic Gate and High-Precision Analog Synapse

We report on a dual-gate transistor with a scaled equivalent oxide thickness (EOT) of approximately 2.4 nm for reconfigurable logic gates and high-precision analog synapses applications. By employing Hf seeding layer dielectric engineering, we were able to deposit a high-k dielectric uniformly and with good coverage on the
$\text{MoS}_{2}$
surface, without causing obvious channel damage. Our device achieved among the lowest subthreshold swing
$(S.S.)$
of approximately 83 mV /dec with top gate (TG) configuration and 63 mV/dec with dual-gate (DG) configuration at a small gate bias. Moreover, we proposed a one-transistor structure that leverages reconfigurable logic gate functions (both ‘AND’ and ‘OR’ gate) and high-performance synapse capabilities (6 bit/cell, 94.17% accuracy), by strategically designing the gate dielectric layers of top and bottom gates.