Enhancing ESD Performance of FinSCRs: Engineering Schemes to Address Current Localization and Failure Current Scalability

This work presents a study on the two critical challenges faced by the conventional FinSCR—electrostatic discharge (ESD) current localization inside a single finger and failure current scalability with the number of fingers—and develops physical insights into the issue. These insights are then used to develop practical solutions/engineering schemes to address these issues to enhance the ESD performance of FinSCR. The nonuniform conduction causing the ESD current localization across a few anode/cathode fins was attributed to high access resistance or inactive fin resistance between the anode/cathode region and the n-well/p-well, which adds to a significantly higher nonuniformity in the base resistance of the parasitic NPN and PNP associated with each of the anode/cathode fins in the CFSCR. To address this, various n-tap and p-tap configurations were explored, and a modified FinSCR (MFSCR) and a scalable variant of MFSCR, i.e., distributed fin tap silicon controlled rectifier (DTFSCR), were proposed. The proposed designs demonstrated over 100% improvement in failure current per unit area, significantly improved failure current scalability with the number of fingers, reduced turn-on time, and improved control on holding voltage and ON-resistance of the SCR. The incorporation of an ESD implant in these architectures was also demonstrated, which showed further improvement. Overall, the proposed engineering schemes offer a promising solution to address ESD current localization and improve failure current scalability in FinSCR devices.