Design and Implementation of Optimized Low Power Pre-Charge Sense Amplifier

In recent time Researchers and VLSI designers are very concerned with low energy consumption because of the exponential improvement in nanoscale technologies. In this proposed research, a stack-based low power reduction technique has been applied in charge sense amplifier utilising the Cadence tool in standard gpdk 45nm technology documentation. Power dissipation of specific sense amplifier topology is the main topic of observations. According to the outcomes of the simulation, the modified charge sense amplifier consumes 123.5094 pW of power. In addition, the proposed application of the stack-based technology in charge sense amplifier results in a reduction of power dissipation by 10-50
^%
when the power supply voltage is 1.8V.