Non-Hermitian Physics-Inspired Voltage-Controlled Oscillators with Resistive Tuning

This paper presents a non-Hermitian physics-inspired voltage-controlled oscillator (VCO) topology, which is termed parity-time-symmetric topology. The VCO consists of two coupled inductor-capacitor (LC) cores with a balanced gain and loss profile. Due to the interplay between the gain/loss and their coupling, an extra degree of freedom is enabled via resistive tuning, which can enhance the frequency tuning range (FTR) beyond the bounds of conventional capacitive or inductive tuning. A silicon prototype is implemented in a standard 130 nm bulk CMOS process with a core area of
$0.15\mathbf{mm}^{2}$
. Experimental results show that it achieves a
$3.1\times$
FTR improvement and 30% phase noise reduction of the baseline VCO with the same amount of capacitive tuning ability.