A Use Case of Iterative Logarithmic Floating-Point Multipliers: Accelerating Histogram Stretching on Programmable SoC

Programmable system-on-chip (SoC) platforms often have a hard-core processor and programmable logic for heterogeneous computing. A custom hardware design implemented with programmable logic accelerates specific operations in an application. This paper applies an area-efficient iterative logarithmic floating-point multiplier to histogram stretching on a programmable SoC platform. Specifically, the floating-point multiplier is implemented with programmable logic, and the hard-core processor on the same platform determines the accuracy and latency of the multiplier by changing the number of iterations used for error correction at runtime. To deploy many multiplier cores working in parallel and have the iterative architecture process streaming data, a higher-level pipelined architecture is proposed. The number of multipliers in this architecture is configurable by changing the maximum number of iterations. For
$352\times 288$
resolution videos, with 250 frames per video, the proposed histogram stretching design reduces the multiplication time by 78% and the total execution time by 13% compared to a design performing exact floating-point multiplications on a hard-core processor.