Readout IC with 40 MSPS in-pixel ADC for future vertex detector upgrades of Large Hadron Collider

We present a prototype smart pixel concept test chip, designed in CMOS 28 nm bulk process, showing a proof-of-concept readout integrated circuit (ROIC) designed for a future Phase III high luminosity upgrade of the large Hadron collider. The presented design employs a synchronous analog-to-digital converter (ADC) for the frontend design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is, therefore, capable of accurately detecting hits occurring in consecutive bunch crossings without off-time registration of events and pileup insensitivity, making it particularly suitable for the innermost layers of the vertex detector. The ROIC consists of a matrix of
$32\times 16$
pixels, each
$25\times 25\ \mu \mathrm{m}^{2}$
in size. Each pixel contains a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The total power consumption is
$\sim 4\ \mu\mathrm{W}$
per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 90 e- with threshold dispersion
$< 45\ \mathrm{e}_{\text{RMS}}^{-}$
, which allows an in-time threshold setting of ≈ 475 e
⁻
.