Low-Cost Hardware Design Approach for Long Short-Term Memory (LSTM)

Long Short-Term Memory (LSTM) has become commonly used for problems with a sequence of data. Hardware implementation of LSTM is a challenge for lightweight applications. This paper proposes an optimized LSTM method with few hardware components. The proposed method utilizes one sigmoid function to perform both input and output gates. The proposed method also utilizes one shared adder instead of two adders to perform the accumulation function for both the input and output gates. This unit performs the two functions in a sequence based on a selection signal which is used as a guide. The proposed method is tested using two datasets: MNIST and IMDB. The simulation results show the proposed method achieves the desired performance in classification compared similarly to the traditional method with a few hardware units. The proposed method is implemented using VHDL on Altera Arria 10 GX FPGA. The simulation results show that the proposed method utilizes fewer resources than the traditional method. The proposed method has a 16% area reduction compared to the traditional method. The proposed method has a power consumption of al.546 W while the traditional method consumes 1.847 W. Thus, the proposed method is suitable for lightweight applications with low hardware costs and desired performance.