A 12T SRAM in-Memory Computing differential current architecture for CNN implementations

This work presents a current mode differential in-memory computing architecture to be used in convolutional neural networks. The architecture is based on CMOS SRAM cells with added circuitry to perform the multiply and accumulate operations required to compute convolutions of
$3\times 3$
masks over
$32\times 32$
pixel images. The convolution is based on a mixed signal approach where analog inputs are multiplied by single bit weights to obtain analog outputs. It has been designed to operate with an input data stream of analog values coming from a CMOS sensor and allows the cascaded connection of several stages as well as the use of the ReLU activation operator The architecture has been synthesized in standard CMOS 180 nm technology and its performance has been tested through device level simulations. The whole circuit operates at a frequency of 10 MHz and achieves and efficiency of 90.9 TOPS/W