A Configurable Multi Source Clock Tree Synthesis For High Frequency Network On Chips

Performance driven designs have led to an increase in the multitude of transistors on an IC following the Moore law. The goal of design engineers is to achieve high frequency operation within the given power budget. Clock tree synthesis distributes the clock signal to the design sinks and plays a vital role in determining the power, performance and area of a design. The H-tree is effective for square shaped blocks in building a clock with minimum skew and latency but fails in constructing an electrically symmetric clock tree for rectilinear and tubular network on chips. In this paper, we present a configurable multi source clock tree synthesis which minimizes the latency, skew, routing resources, power consumption and on chip variations. On examining various network on chips and performing several iterations the average improvement values are as follows. Latency decreased by 35.32%, skew reduced by 47.51 %, clock power improved by 15.17%, routing resources were saved by 15.41 % and number of hold buffers reduced by 16.53%.